Zynq 7000 All Programmable SoC Software Developers Guide

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Programmable SoC Software Developers Guide UG821 v12 0 September 30 2015 Zynq 7000 AP SoC SWDG www xilinx com 2 UG821 v12 0 September 30 2015 Revision History The following table shows the revision history for this document Date Version Revision 09 30 2015 12 0 Removed LibXil SKey and LibXil RSA Added references to the library locations 06 24 2015 11 0 Updated Appendix B LibXil SKey

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Revision History, The following table shows the revision history for this document. Date Version Revision, 09 30 2015 12 0 Removed LibXil SKey and LibXil RSA Added references to the library locations. 06 24 2015 11 0 Updated Appendix B LibXil SKey for Zynq 7000 AP SoC Devices v2 1. Changed Vivado Device Programmer to Vivado hardware manager. Changed Platform Reference Manual reference to Generating Software Platforms. Updated Bootgen options to match h in Vivado Tcl Console in Table A 3. 04 01 2015 10 1 Added miscellaneous references throughout the document. Updated BIF File Attributes,Added Bootgen Command Options. Updated Partition Attribute Bits, 06 04 2014 9 0 Updated Bootgen to remove the i option in Bootgen Command Options. Throughout document added cross references and updated links in Appendix D. Additional Resources and Legal Notices,Added definitions for RSA and SHA 2.
Removed reference to UG652,Changed AP to PS on page 23. 04 02 2014 8 0 Initial release for 2014 1, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Table of Contents, Chapter 1 Introduction to Programming with Zynq 7000 AP SoC Devices. Overview 5,Introduction 5,Architectural Decisions 6. Operating System OS Considerations 7,Chapter 2 Software Application Development Flows.
Introduction 9,Software Tools Overview 10,Bare Metal Device Driver Architecture 14. Bare Metal Application Development 17,Linux Application Development 21. Additional Information 26,Chapter 3 Boot and Configuration. Overview 27,Boot Modes 28,Boot Stages 28,Boot Image Creation 48. BootROM Header Format 51,Chapter 4 Linux,Introduction 52.
Git Server and Gitk Command 52,Linux BSP Contents 53. Appendix A Using Bootgen,Introduction 55,BIF File Syntax 55. Initialization Pairs and the INT File Attribute 58. Encryption Overview 59,Authentication Overview 60, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Bootgen Command Options 61. Image Header Table 63,Partition Header Table 64,Partition Attribute Bits 65.
Image Header 66,Appendix B Additional Resources and Legal Notices. Xilinx Resources 67,Solution Centers 67,References 67. Please Read Important Legal Notices 68, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Introduction to Programming with. Zynq 7000 AP SoC Devices, This document summarizes the software centric information required for designing with.
Xilinx Zynq 7000 All Programmable SoC devices It assumes that you are. Experienced with embedded software design,Familiar with ARM development tools. Familiar with Xilinx FPGA devices intellectual property IP cores development tools. and tool environments,Introduction, The addition of extensibility of the SoC for both hardware and software programmability. imposes new requirements on design flows for both hardware and software. Certain hardware features are unique to Xilinx such as hardware co simulation and. co debug functionality that make it possible to verify custom logic implemented on. Zynq 7000 AP SoC devices or in a logic simulation environment while applications execute. on a Zynq 7000 AP SoC processor on a physical board or an emulator. For a step by step explanation on designing a Zynq based embedded system see the. following documents, Vivado Design Suite Tutorial Embedded Processor Hardware Design UG940 Ref 6. Vivado Design Suite User Guide Embedded Processor Hardware Design UG898 Ref 5. Vivado Design Suite Tutorial Zynq 7000 All Programmable SoC Embedded Design. UG1165 Ref 16, VIDEO See Enabling Smarter Systems for quick take videos on the Zynq 7000 AP SoC devices. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015, Chapter 1 Introduction to Programming with Zynq 7000 AP SoC Devices.
Architectural Decisions, You must make several architectural decisions before beginning embedded development. on applications to run on the Zynq 7000 AP SoC, Because the Zynq 7000 AP SoC devices have dual core ARM Cortex A9 processors you. must determine whether to use Asymmetric Multiprocessing AMP or Symmetric. Multiprocessing SMP, The same decision must be made for all embedded software projects which operating. system s to use if any This introduction defines both AMP and SMP and provides an. assessment of the trade offs and concerns with each method. Multiprocessing Considerations, The following subsections describe the two multiprocessing considerations. Asymmetric Multiprocessing, Asymmetric multiprocessing AMP is a processing model in which each processor in a.
multiple processor system executes a different operating system image while sharing the. same physical memory Each image can be of the same operating system but more. typically each image is a different operating system complementing the other OS with. different characteristics, A full featured operating system such as Linux lets you connect to the outside world. through networking and user interfaces, A smaller light weight operating system can be more efficient with respect to memory. and real time operations, A typical example is running Linux as the primary operating system along with a smaller. light weight operating system such as FreeRTOS or a bare metal system which is described. in Chapter 4 Linux as the secondary operating system. The division of system devices such as the UART timer counter and Ethernet between the. processors is a critical element in system design In general. Most devices must be dedicated to their assigned processor. The interrupt controller is designed to be shared with multiple processors. One processor is designated as the interrupt controller master because it initializes the. interrupt controller, Communication between processors is a key element that allows both operating systems to. be effective It can be achieved in many different ways including inter processor interrupts. shared memory and message passing, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback.
UG821 v12 0 September 30 2015, Chapter 1 Introduction to Programming with Zynq 7000 AP SoC Devices. Symmetric Multiprocessing, Symmetric multiprocessing SMP is a processing model in which each processor in a. multiple processor system executes a single operating system image The scheduler of the. operating system is responsible for scheduling processes on each processor. This is an efficient processing model when the selected single operating system meets the. system requirements The operating system uses the processing power of multiple. processors automatically and is consequently transparent to the end user Programmers. Specify a specific processor to execute a process,Handle interrupts with any available processor. Designate one processor as the master for system initialization and booting other. processors,Operating System OS Considerations,Bare Metal System. Bare metal refers to a software system without an operating system This software system. typically does not need many features such as networking that are provided by an. operating system An operating system consumes some small amount of processor. throughput and tends to be less deterministic than simple software systems Some system. designs might not allow the overhead and lack of determinism of an operating system As. processing speed has continued to increase for embedded processing the overhead of an. operating system has become mostly negligible in many system designs Some designers. choose not to use an operating system due to system complexity. Operating System Linux, Linux is an open source operating system used in many embedded designs It is available.
from many vendors as a distribution or it can be built from the open source repositories. Linux is not inherently a real time operating system but it has taken on more real time. characteristics, It is a full featured operating system that takes advantage of the memory management unit. MMU in the processor and is consequently regarded as a protected operating system. Linux also provides SMP capabilities to take advantage of multiple processors. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015, Chapter 1 Introduction to Programming with Zynq 7000 AP SoC Devices. Real Time Operating System, Some system designers use a real time operating system RTOS from Xilinx third party. An RTOS offers the deterministic and predictable responsiveness required by timing. sensitive applications and systems For information on the latest third party tools contact. your nearest Xilinx office,Zynq 7000 Operating Systems From Partners. You can choose you own favorite embedded solutions based on past experience new. standards unique requirements and legacy designs as well as corporate agreements. For a detailed list of operating systems supported on Zynq 7000 devices from Xilinx. partners see the Zynq 7000 Ecosystem page, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback.
UG821 v12 0 September 30 2015,Software Application Development Flows. Introduction, The Zynq 7000 All Programmable AP SoC software application development flows let. you create software applications using a unified set of Xilinx tools and leverage a broad. range of tools offered by third party vendors for the ARM Cortex A9 processors. This chapter focuses on Xilinx tools and flows however the concepts are generally. applicable to third party tools and the Zynq 7000 AP SoC device solutions incorporate. familiar components such as an Eclipse based integrated development environment IDE. and the GNU compiler toolchain, This chapter also provides an overview of bare metal and Linux software application. development flows using Xilinx tools which mirror support available for other Xilinx. embedded processors with differences as noted This chapter also references boot device. configuration and OS usage within the context of application development flows Those. topics are covered in depth in other chapters and references to other material. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows. The following figure shows a block diagram of the Zynq 7000 AP SoC device processor. X Ref Target Figure 2 1,3URFHVVLQJ 6 VWHP,3HULSKHUDOV ORFN SSOLFDWLRQ 3URFHVVRU 8QLW.
86 5HVHW 7,27 38 DQG 1 21 QJLQH 38 DQG 1 21 QJLQH,50 RUWH 50 RUWH. 23 008 008,LJD LJ 6 VWHP 38 38,LJD 6 QWHUFRQQHFW HYHO. 6 RQWURO DFKH DFKH DFKH DFKH,6 54 6QRRS RQWUROOHU 8QLW. 3 2 0 DFKH RQWUROOHU,8 57 KDQQHO,8 57 QWHUFRQQHFW,QWHUFRQQHFW 65 0. 63 QWHUFRQQHFW 0HPRU,63 QWHUIDFHV,RUH6LJKW 5,QWHUIDFHV RPSRQHQWV 3 5.
125 3URFHVVLQJ 3URFHVVLQJ,6 VWHP 6 VWHP 3,1 1 0DVWHU 6ODYH 9 3URJUDPPDEOH RJLF WR 0HPRU. 4 63 QWHUFRQQHFW QWHUFRQQHFW QWHUFRQQHFW,0 2 0 54 RQILJ 3. 70 HJHQG 3URJUDPPDEOH RJLF 6HOHFW 2,UURZ GLUHFWLRQ VKRZV FRQWURO PDVWHU WR VODYH. GDWD IORZV LQ ERWK GLUHFWLRQV,ELW ELW ELW ELW ELW 3 ELW XVWRP 3 H. Figure 2 1 Zynq 7000 AP SoC Processing System High Level Diagram. Software Tools Overview, The coupling of ARM based Processing System PS and Programmable Logic PL creates.
unique opportunities to add custom peripherals and co processors Custom logic. implemented in the PL can be used to accelerate time critical software functions reduce. application latency reduce system power or provide solution specific hardware features. The addition of hardware programmability to the hardware and software interface imposes. new requirements on design flows Certain hardware features are unique to Xilinx such as. hardware co simulation and co debug functionality that make it possible to verify custom. logic implemented on Zynq 7000 AP SoC devices or in a logic simulation environment while. applications execute on a Zynq 7000 AP SoC device processor on a physical board or an. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows. Xilinx provides design tools for developing and debugging software applications for. Zynq 7000 AP SoC devices that include,Software IDE. GNU based compiler toolchain,JTAG debugger,Associated utilities. These tools let you develop both,Bare metal applications that do not require an OS. Applications for the open source Linux OS, Custom logic and user software can run various combinations of physical hardware or.
simulation with the ability to monitor hardware events For example. Custom logic running in hardware or in a simulation tool. User software running on the target or in a software emulator. PL and processor cross triggering on events, Software solutions are also available from third party sources that support Cortex A9. processors including but not limited to,Software IDEs. Compiler toolchains,Debug and trace tools,Embedded OS and software libraries. Simulators,Models and virtual prototyping tools, Third party tool solutions vary in the level of integration and direct support for Zynq 7000. AP SoC devices Xilinx does not provide tools that target Kernel development and debug. but those tools can be obtained from third party vendors. The following subsections provide a summary of the available Xilinx development tools. Tools are available on 32 and 64 bit Windows and x86 Linux host computing platforms. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows.
Hardware Configuration Tool, Xilinx provides the Vivado IP integrator which lets you use a block diagram to configure IP. that is related to the PL and the Zynq 7000 AP SoC device processor. The Vivado Design Suite IP integrator provides a block diagram for the Zynq 7000 AP SoC. wherein you can set Programmable Logic PL information in an XML file INIT files. h c and tcl which are then used by software design tools to create and configure. Board Support Package BSP libraries infer compiler options define JTAG settings and. automate other operations that require information about the hardware. For more information see the following documents, Vivado Design User Guide Embedded Processor Hardware Design UG898 Ref 5. Vivado Design Suite Tutorial Embedded Processor Hardware Design UG940 Ref 6. Vivado Design Suite User Guide Using the Vivado IDE UG893 Ref 7. Vivado Design Suite User Guide Designing IP Subsystems Using IP Integrator UG994. Software Development Kit, The Xilinx Software Development Kit SDK provides a complete environment for creating. software applications targeted for Xilinx embedded processors It includes a GNU based. compiler toolchain GCC compiler GDB debugger utilities and libraries JTAG debugger. flash programmer drivers for Xilinx IPs and bare metal board support packages. middleware libraries for application specific functions and an IDE for C C bare metal. and Linux application development and debugging Based upon the open source Eclipse. platform SDK incorporates the C C Development Toolkit CDT Features include. C C code editor and compilation environment,Project management. Application build configuration and automatic makefile generation. Error navigation, Integrated environment for debugging and profiling embedded targets.
Additional functionality available using third party plug ins including source code. version control,SDK Availability, SDK is available as a download with the Vivado Design Suite and as a standalone. application SDK also includes an application template for creating a First Stage Bootloader. FSBL as well as a graphical interface for building a boot image. Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows. SDK contains a complete help system that describes concepts tasks and reference. information See the Xilinx Software Development Kit Help UG782 Ref 14 for more. information, You can launch SDK from Vivado when you export a hardware definition as shown in. Figure 2 2,X Ref Target Figure 2 2,Figure 2 2 Export Hardware for SDK Dialog Box. System Performance Analysis, The Xilinx Software Debugger XSDB uses a System Performance Monitor SPM for.
See the following links for more information regarding SPM Ref 15. Chapter 3 in the Xilinx Software Development Kit SDK System Performance UG1145. Chapter 5 in the Xilinx Software Development Kit SDK System Performance UG1145. Also see System Performance Analysis of an All Programmable SoC XAPP1219 Ref 17. Sourcery CodeBench Lite Edition for Xilinx Cortex A9 Compiler Toolchain. SDK includes the Sourcery CodeBench Lite Edition for Xilinx Cortex A9 compiler toolchain. for bare metal Embedded Application Binary Interface EABI and Linux application. development, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows. The Xilinx Sourcery CodeBench Lite toolchain in SDK contains the same GNU tools libraries. and documentation as the standard Sourcery CodeBench Lite Edition EABI and Linux compiler. toolchains but adds the following enhancements, Default toolchain settings for the Xilinx Cortex A9 processors. Bare metal EABI start up support and default linker scripts for the Xilinx Cortex A9. processors, Vector Floating Point VFP and NEON optimized libraries. Analysis Tools,Vivado Lab Tool, The Vivado IDE has integrated debugging capability See Vivado Design Suite User Guide.
Programming and Debugging UG908 Ref 11 for more information. System Generator for DSP, The System Generator for DSP tool can be used to develop DSP and data flow centric. hardware based coprocessors working within the MATLAB Simulink environment. System Generator supports rapid simulation of the DSP hardware reducing overall. development time and automates the generation of co processors that can be connected. to the PS The SDK co debug feature lets you run and debug programs running on the. processor in SDK while retaining visibility and control over the hardware under. development in System Generator,Bare Metal Device Driver Architecture. The bare metal device drivers are designed with a layered architecture as shown in. Figure 2 3 page 15 The layered architecture accommodates the many use cases of device. drivers while at the same time providing portability across operating systems toolsets and. processors, The layered architecture provides seamless integration with. A Layer 2 RTOS Adapter an abstract device driver interface that is full featured and. portable across operating systems,Processors Layer 1 Device Driver. A direct hardware interface for simple use cases or those wishing to develop a custom. device driver,The following subsections describe the layers.
Zynq 7000 AP SoC SWDG www xilinx com Send Feedback. UG821 v12 0 September 30 2015,Chapter 2 Software Application Development Flows. IMPORTANT The direct hardware interface does not add additional overhead to the device driver. function call overhead as it is typically implemented as a set of manifest constants and macros. X Ref Target Figure 2 3,XAMPLE PPLICATIONS 5SER PPLICATION. LIBXIL A PTIONAL AYER 24 3 DAPTER,IBRARIES AYER EVICE RIVER. IRECT ARDWARE NTERFACE,8ILINX FFERING IN 3,5SER ESIGN. Figure 2 3 Bare Metal Drivers Architecture, Zynq 7000 AP SoC SWDG www xilinx com Send Feedback.

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